Neuromorphic Engineering Book
  • Welcome
  • Preliminaries
    • About the author
    • Preface
    • A tale about passion and fear
    • Before we begin
  • I. Introduction
    • 1. Introducing the perspective of the scientist
      • From the neuron doctrine to emergent behavior
      • Brain modeling
      • Take away lessons
    • 2. Introducing the perspective of the computer architect
      • Limits of integrated circuits
      • Emerging computing paradigms
      • Brain-inspired hardware
      • Take away lessons
      • Errata
    • 3. Introducing the perspective of the algorithm designer
      • From artificial to spiking neural networks
      • Neuromorphic software development
      • Take home lessons
  • II. Scientist perspective
    • 4. Biological description of neuronal dynamics
      • Potentials, spikes and power estimation
      • Take away lessons
      • Errata
    • 5. Models of point neuronal dynamic
      • Tutorial - models of point neuronal processes
        • The leaky integrate and fire model
        • The Izhikevich neuron model
        • The Hodgkin-Huxley neuron model
      • Synapse modeling and point neurons
      • Case study: a SNN for perceptual filling-in
      • Take away lessons
    • 6. Models of morphologically detailed neurons
      • Morphologically detailed modeling
      • The cable equation
      • The compartmental model
      • Case study: direction-selective SAC
      • Take away lessons
    • 7. Models of network dynamic and learning
      • Circuit taxonomy, reconstruction, and simulation
      • Case study: SACs' lateral inhibition in direction selectivity
      • Neuromorphic and biological learning
      • Take away lessons
      • Errate
  • III. Architect perspective
    • 8. Neuromorphic Hardware
      • Transistors and micro-power circuitry
      • The silicon neuron
      • Case study: hardware - software co-synthesis
      • Take away lessons
    • 9. Communication and hybrid circuit design
      • Neural architectures
      • Take away lessons
    • 10. In-memory computing with memristors
      • Memristive computing
      • Take away lessons
      • Errata
  • IV. Algorithm designer perspective
    • 11. Introduction to neuromorphic programming
      • Theory and neuromorphic programming
      • Take away lessons
    • 12. The neural engineering framework
      • NEF: Representation
      • NEF: Transformation
      • NEF: Dynamics
      • Case study: motion detection using oscillation interference
      • Take away lessons
      • Errate
    • 13. Learning spiking neural networks
      • Learning with SNN
      • Take away lessons
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  1. III. Architect perspective
  2. 9. Communication and hybrid circuit design

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Fully-dedicated design: A network connectivity scheme in which a dedicated physical wire is allocated to each neuron-synapse connection. In a fully dedicated neuron connectivity scheme, a system with N neurons has N axons and N2 synapses. Neuron i is indicated with Ni, axons coming out of neuron i is indicated with axi and a synapse connecting neuron i with neuron j is indicated with Sij.

Address Event Representation: A neuromorphic inter/intra chip communication protocol in which spike-triggered events are multiplexed on a single communication bus. With address event representation, spikes are encoded with a neuron address and multiplexed on a communication line by an encoding circuit. Spikes are distributed to their targets by an encoding circuit.

Hybrid neuromorphic design: A neuromorphic design in which computation is held physically with analog circuitry, and communication is held digitally (usually with AER).

Shared axon design: A network connectivity scheme in which axons are shared among neurons, enabling log2N wires to support fully connected N neurons. In a shared axon neuron connectivity scheme, neuron connectivity is made via an encoder and decoder circuits which implement AER. This architecture features N neurons, log2N axons, and N^2 synapses.

Digital neuromorphic design: A digital neuromorphic system in which both computation and communication are held digitally.

Shared synapse design: A network connectivity scheme which is realized with memory. In a shared synapse neuron connectivity scheme, neuron connectivity is made via a memory chip which holds a programmable address and weight mapping. This architecture features N neurons, log2N axons, and N synapses.

Tree arbitration: spiking neurons compete for a shared communication line via hierarchical binary arbitration units. Arbitration takes an overhead of O(log2N) operations.

TrueNorth core: comprised of N neurons, connected with N axons through binary synapses. Spikes are encoded with packets and introduced to a router which can route spike events to the same or a foreign core’s axons. Here, a spike from a foreign core activates axon 2 which is connected to neurons 2 and 4. As a response, each neuron emits a spike (assuming that the neurons’ initial states permit it). In this schematic, both spikes are routed back to axon 3.

TrueNorth system: TrueNorth system schematic, showing how spikes propagate through two connected cores in two consecutive time steps. At t1, axon 2 of one core is activated, causing neurons 2 and 4 to emit spikes. One spike is routed back to the same core at axon 3, activating neuron 2 at t2. The second spike is routed to the second core at axon 3, activating neurons 1 and 2 at t2. At t2, the generated spike at the first core is routed to axon 1 of the second core. Simultaneously, two spikes are generated by the second core. One of them is routed back to the same core at axon 4 and the other is routed off-core.