> For the complete documentation index, see [llms.txt](https://elishai.gitbook.io/neuromorphic-engineering/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://elishai.gitbook.io/neuromorphic-engineering/architect-perspective/communication-and-hybrid-circuit-design/take-away-lessons.md).

# Take away lessons

**Fully-dedicated design**: A network connectivity scheme in which a dedicated physical wire is allocated to each neuron-synapse connection. In a fully dedicated neuron connectivity scheme, a system with N neurons has N axons and N2 synapses. Neuron i is indicated with Ni, axons coming out of neuron i is indicated with axi and a synapse connecting neuron i with neuron j is indicated with Sij.

![](https://1487620879-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MiS7NytljlKs-2Yccqw%2F-Mj4R7A4YdDW-WV8q_h6%2F-Mj4UW_bXyYVaeZFAx7w%2FScreen%20Shot%202021-09-08%20at%2015.59.36.png?alt=media\&token=9a9e8e1a-241b-4cb8-9baa-7793b4140880)

**Address Event Representation**: A neuromorphic inter/intra chip communication protocol in which spike-triggered events are multiplexed on a single communication bus. With address event representation, spikes are encoded with a neuron address and multiplexed on a communication line by an encoding circuit. Spikes are distributed to their targets by an encoding circuit.

![](https://1487620879-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MiS7NytljlKs-2Yccqw%2F-Mj4R7A4YdDW-WV8q_h6%2F-Mj4UmrPhBsRWbOllxna%2FScreen%20Shot%202021-09-08%20at%2016.00.39.png?alt=media\&token=d450f92a-0087-4cc6-95c6-a4f4778934b5)

**Hybrid neuromorphic design:** A neuromorphic design in which computation is held physically with analog circuitry, and communication is held digitally (usually with AER).

**Shared axon design**: A network connectivity scheme in which axons are shared among neurons, enabling log2N wires to support fully connected N neurons. In a shared axon neuron connectivity scheme, neuron connectivity is made via an encoder and decoder circuits which implement AER. This architecture features N neurons, log2N axons, and N^2 synapses.

![](https://1487620879-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MiS7NytljlKs-2Yccqw%2F-Mj4R7A4YdDW-WV8q_h6%2F-Mj4V0WS7D_DiOj6O4_5%2FScreen%20Shot%202021-09-08%20at%2016.01.26.png?alt=media\&token=2a5f7925-932d-4f0b-a844-5d754f45b4c7)

**Digital neuromorphic design**: A digital neuromorphic system in which both computation and communication are held digitally.

**Shared synapse design**: A network connectivity scheme which is realized with memory. In a shared synapse neuron connectivity scheme, neuron connectivity is made via a memory chip which holds a programmable address and weight mapping. This architecture features N neurons, log2N axons, and N synapses.

![](https://1487620879-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MiS7NytljlKs-2Yccqw%2F-Mj4R7A4YdDW-WV8q_h6%2F-Mj4VOVk4CHtfLXkAJVy%2FScreen%20Shot%202021-09-08%20at%2016.03.01.png?alt=media\&token=9790b2e8-dddb-42cb-860a-9e34723c0b80)

**Tree arbitration**: spiking neurons compete for a shared communication line via hierarchical binary arbitration units. Arbitration takes an overhead of O(log2N) operations.

![](https://1487620879-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MiS7NytljlKs-2Yccqw%2F-Mj4R7A4YdDW-WV8q_h6%2F-Mj4VhvP0ki5MFQOkR_L%2FScreen%20Shot%202021-09-08%20at%2016.04.50.png?alt=media\&token=8e873679-0561-4ae8-b91f-50c4a9c708a0)

**TrueNorth core**:  comprised of N neurons, connected with N axons through binary synapses. Spikes are encoded with packets and introduced to a router which can route spike events to the same or a foreign core’s axons. Here, a spike from a foreign core activates axon 2 which is connected to neurons 2 and 4. As a response, each neuron emits a spike (assuming that the neurons’ initial states permit it). In this schematic, both spikes are routed back to axon 3.

![](https://1487620879-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MiS7NytljlKs-2Yccqw%2F-Mj4R7A4YdDW-WV8q_h6%2F-Mj4WPeXUgFeArAZetZn%2FScreen%20Shot%202021-09-08%20at%2016.07.46.png?alt=media\&token=982b50df-4ced-4089-a738-22fc7d73c507)

**TrueNorth system:** TrueNorth system schematic, showing how spikes propagate through two connected cores in two consecutive time steps. At t1, axon 2 of one core is activated, causing neurons 2 and 4 to emit spikes. One spike is routed back to the same core at axon 3, activating neuron 2 at t2. The second spike is routed to the second core at axon 3, activating neurons 1 and 2 at t2. At t2, the generated spike at the first core is routed to axon 1 of the second core. Simultaneously, two spikes are generated by the second core. One of them is routed back to the same core at axon 4 and the other is routed off-core.

![](https://1487620879-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MiS7NytljlKs-2Yccqw%2F-Mj4R7A4YdDW-WV8q_h6%2F-Mj4Whmuxh6YgmggpuIu%2FScreen%20Shot%202021-09-08%20at%2016.09.11.png?alt=media\&token=6b3e03ab-e9f3-4e76-a3b4-1d5324d82e41)