> For the complete documentation index, see [llms.txt](https://elishai.gitbook.io/neuromorphic-engineering/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://elishai.gitbook.io/neuromorphic-engineering/architect-perspective/10.-in-memory-computing-with-memristors/take-away-lessons.md).

# Take away lessons

**Circuit elements:** The three fundamental circuit elements are the resistor, capacitor, and the inductor. These elements relate current, voltage, charge, and flux linkage. Five pairwise connections between these elements are well-known. The sixth missing link is the memristor which relates charge to flux linkage.

![](https://1487620879-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MiS7NytljlKs-2Yccqw%2F-Mj4R7A4YdDW-WV8q_h6%2F-Mj4ZkOu-ePAZRc1osAH%2FScreen%20Shot%202021-09-08%20at%2016.10.59.png?alt=media\&token=4e05e394-ebcc-4e76-8f0c-8dfddf3980d4)

**Memristor**: A non-linear two-terminal fundamental circuit element which relates electric charge and magnetic flux linkage.

**The memristor's V-I curve:** exhibits an hysteresis effect, caus- ing its memristance to change non-linearly with respect to the applied voltage. The memristor’s memristance depends on the previous flux of charge the memristor experienced.

![](https://1487620879-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MiS7NytljlKs-2Yccqw%2F-Mj4R7A4YdDW-WV8q_h6%2F-Mj4_njb_e7UR-9nGsJt%2FScreen%20Shot%202021-09-08%20at%2016.27.04.png?alt=media\&token=ba74b6eb-0014-4db3-8fe6-92999f7d84d9)

While the memristor’s memristance changes in a non-linear pattern with respect to the applied voltage, as the frequency of the input voltage increases, this pattern becomes more linear.

![](https://1487620879-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MiS7NytljlKs-2Yccqw%2F-Mj4R7A4YdDW-WV8q_h6%2F-Mj4_fzfgXe5dm7l_mAI%2FScreen%20Shot%202021-09-08%20at%2016.26.31.png?alt=media\&token=04a0671f-4b08-4985-a7b2-28ce8113f476)

The memristor’s memristance can be used to represent a particular memory state, thus enabling a memristance-memory mapping. Here, the memristance values (R00, R01, R10, R11) represent four binary states ((00)2, (01)2, (10)2, (11)2), respectively.

![](https://1487620879-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MiS7NytljlKs-2Yccqw%2F-Mj4R7A4YdDW-WV8q_h6%2F-Mj4bNCFfPcf7ojQ1gs3%2FScreen%20Shot%202021-09-08%20at%2016.33.56.png?alt=media\&token=69a7efe4-ceba-416f-9469-4c45ed9821f1)

**The memristor-CMOS crossbar:** provides an efficient fully connected neuronal architecture in which the top layered wires are connected with an intermediate memristive layer to wires in the bottom layer.

![](https://1487620879-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MiS7NytljlKs-2Yccqw%2F-Mj4bPiY9pG-xHy9iZYZ%2F-Mj4bdLln9zTA2tWBPvC%2FScreen%20Shot%202021-09-08%20at%2016.35.06.png?alt=media\&token=0ccb353c-1b1f-45d0-b6ee-2d55d68ef3fa)